1. Field of the Invention
The present invention relates generally to a method for fabricating semiconductor memory devices. More specifically, the present invention relates to a process for planarizing the array top oxide (ATO) in vertical metal-oxide-semiconductor field-effect transistor (MOSFET) dynamic random access memory (DRAM) arrays.
2. Description of the Prior Art
Trench-capacitor DRAM devices are known in the art. Typically, a trench-storage capacitor consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor. DRAM cells using trench-storage capacitors are particularly well suited for the integration of vertical MOSFETs, since a portion of the wall of the trench above the storage capacitor is utilized for the channel, while the bitline wiring is formed above the surface of the silicon substrate. When a transistor is built along the walls of a trench, the channel length is decoupled from the minimum lithographic feature size and the size of the memory cell.
In the present process for memory cell fabrication in vertical MOSFET DRAM arrays, removal of the etch stop nitride liner from the array results in thinning of the underlying top oxide which is intended to provide insulation between the silicon substrate and the word lines to be formed subsequently. Thinning of the top oxide results in a higher than desired incidence of word line to substrate shorts and/or leakage. Furthermore, thinning of the top oxide may result in the formation of divots in the array gate conductor (GC) polysilicon in the top portion of the deep trench, due to gate stack overetch. Divots in the array GC polysilicon which are deeper than the bit line diffusion junction result in non-functional array MOSFETs due to gate underlap.
A known process called ARC-RIE process is typically used to planarize array top oxide (ATO) at the stage after finishing the substrate active area definition and insulations in the middle of fabrication of vertical transistor DRAM devices. In the ARC-RIE process, an anti-reflection coating (ARC) is first coated over the entire surface of the substrate having thereon a plurality of trench capacitors, active areas, and shallow trench isolations (STI). A reflow process is then carried out, followed by reactive ion etching (RIE) to etch away a thickness of the ARC film. However, one problem with the conventional ARC-RIE process is that the height difference at the transition region between the support region and array region cannot be compensated by the ARC-RIE process, thereby generating ATO residue defects, which usually cause word line open. Moreover, the conventional ARC-RIE process cannot overcome poly/nitride stack corrosion during the stripping of pad nitride. This is because silicon nitride of the poly/nitride stack has low resistance to buffer HF (BHF) etchant used to etch pad nitride in the support region, thus leads to poly string problems.
In view of the above discussion, it becomes apparent that there is a need for an improved planarization process at the stage after finishing the substrate active area definition and insulations in the middle of fabrication of vertical transistor DRAM devices to solve the above-mentioned problems.